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Parasitic Capacitance of Through Hole in PCB Design
Dec 07, 2018


Parasitic Capacitance of Through Hole in PCB Design


There is a parasitic capacitance to the ground for via itself, if know the isolation hole diameter is D2 in the ground layer for the via, the diameter of the via welding pad is D1, PCB thickness is T, board base material dielectric constant is ε, then the parasitic capacitance of the via approximation in: C = 1.41 epsilon TD1 / (- D1, D2), the parasitic capacitance of the through-hole will mainly affect the circuit by extending the rising time of the signal and reducing the speed of the circuit. 

For example, for a PCB board with a thickness of 50Mil, the through-hole with an inner diameter of 10Mil and a welding pad diameter is 20Mil,if the distance between the welding pad and the copper laying area is 32Mil, the parasitic capacitance of the hole can be approximately calculated by the above formula: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, and the rise time variation caused by this part of capacitance is: T10-90 =2.2C(Z0/2)=2.2x0.517x(55/2)=31.28ps. From these values, it can be seen that although the effect of the slow rise delay caused by the parasitic capacitance of a single via is not obvious, if the hole is used repeatedly in the tracking to switch between layers, the designer should carefully consider.